"This book brings together new developments in the area of spin-engineered MOSFETs using high-mobility substrates such as SIGe, strained-Si, germanium-on-insulator, and III-V semiconductors. The authors cover the materials aspects, principles, design, fabrication, and applications of advanced devices. They present a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization"-- Provided by publisher.

Includes bibliographical references and index.

Print version record.

1. Introduction -- 2. Substrate-induced strain engineering in CMOS technology -- 3. Process-induced stress engineering in CMOS technology -- 4. Electronic properties of strain-engineered semiconductors -- 5. Strain-engineered MOSFETs -- 6. Noise in strain-engineered devices / C. Mukherjee -- 7. Technology CAD of strain-engineered MOSFETs -- 8. Reliability and degradation of strain-engineered MOSFETs -- 9. Process compact modelling of strain-engineered MOSFETs -- 10. Process-aware design of strain-engineered MOSFETs -- 11. Conclusions.

Open Access EbpS